Sundance SMT368 Manual do Utilizador

Sundance Multiprocessor Technology Limited Form : QCF42 User Manual Date : 6 July 2006 Unit / Module Description: Virtex 4 FPGA module Unit / Modul

The ZBTRAM is designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice-versa. The d

Figure 5: SHB Constraints file data signal names 4.1.8 Sundance Low voltage differential signals Bus 1 x 60 LVDS pairs I/O connections between the

4.1.9 TIM Connectors TIM connectors provide 4 ComPorts to the FPGA: ComPort_0, 1, 3 and 4. They allow interfacing to Sundance modules or to a host by

Figure 7: Schematics of the External Clock I/O Constraints file signal names: BOARDCLK On-board oscillator input to the FPGA (pin AF10) EXT_CLK

The following table describes the settings for the jumper SW1 according to the various FPGA configuration modes: Configuration SW1 PositionPOS3 POS2

4.2.3 TIM config The TIM config is a special reset feature. This signal comes from the TIM connector (P1), pin 74, and it is available to the CPLD.

4.3.3 Programming the Xilinx PROM DO NOT fit the SLB mezzanine before programming the PROM via JTAG. It makes the JTAG fail. (It does not damage the

Right click on the PROM icon and select Program from the menu. Next, select the same options as per Figure 10.and click O.K. on the 2 dialog windows.

Figure 11: PROM programming. It can take more than 2 minutes… User Manual SMT368 Page 18 of 24 Last Edited: 31/12/2008 13:53

A successful programming is indicated as per Figure 12. Figure 12: Programming succeeded User Manual SMT368 Page 19 of 24 L

Revision History Issue Changes Made Date Initials 2.0 New release 04/09/2006 SM 2.1 Added: weight characteristic 21/09/2006 SM 2.2 Added detai

Sundance Multiprocessor Technology Limited Form : QCF42 User Manual Date : 6 July 2006 5 Footprint 5.1 Top View User Manual SMT368 Last Edited:

Sundance Multiprocessor Technology Limited Form : QCF42 User Manual Date : 6 July 2006 5.2 Bottom View Figure 14: PCB – Bottom view 6 Pinout 6.1

Note: An adapter is necessary to connect the JTAG Header JP1 to the Xilinx Parallel cable IV. Please ask your Sundance technical or sales person for

Figure 17: Boundary JTAG chain (Xilinx iMPACT) 6.4 I/Os Header The TTL I/Os header is a 2mm pitch pin-socket, and it is referenced JP3. Signal Pin P

8 Physical Properties Dimensions 106.68mm x 63.5mm 4.2’’ x 2.5’’ Weight 50g. Supply Voltages Supply Current +12V +5V +3.3V -5V -12V

Table of Contents 1 Introduction...6 2 Related Documents

6.3 JTAG Header ...21 6.4 I/Os Header..

Table of Figures and Tables Figure 1: Block Diagram...

1 Introduction The SMT368 is a single-size module based on a Virtex-4 FPGA (XC4VSX35) and provides the following features: • On-board ZBTRAM memory,

3 Acronyms, Abbreviations and Definitions 3.1 Acronyms and Abbreviations TIM Texas Instruments Module DSP Digital Signal Processor FPGA Field Pro

4 Functional Description The module is conformed to the Texas Instruments Module standard for single-size modules. It sits on a carrier board that pr

4.1.3 FPGA Xilinx Virtex-4 XC4VSX35™ - Device package FFG668. This device has 448 I/O-pin BGA package with a -10 speed grade. It contains up to 34,56