Sundance SMT941 Manual do Utilizador

Sundance Multiprocessor Technology Limited User Manual Form : QCF42 Date : 11 February 2009 User Manual SMT941 Last Edited: 23/08/2011 17:24:00 U

User Manual SMT941 Page 10 of 43 Last Edited: 23/08/2011 17:24:00 2.2.2 Clock structure The following diagram shows the clock structure o

User Manual SMT941 Page 11 of 43 Last Edited: 23/08/2011 17:24:00 Input Voltage Level 1 – 3.3 Volts peak-to-peak (AC-coupled) Frequency Range 0 – 10

User Manual SMT941 Page 12 of 43 Last Edited: 23/08/2011 17:24:00 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3 Command 3 Command 2 Command

User Manual SMT941 Page 13 of 43 Last Edited: 23/08/2011 17:24:00 0x29 Clock Register 0x19. Read-back (FPGA Register) Clock Register 0x19. 0x2A Cloc

User Manual SMT941 Page 14 of 43 Last Edited: 23/08/2011 17:24:00 Setting Bit 5 Description chab trigger selection 0 0 Trigger from control register

User Manual SMT941 Page 15 of 43 Last Edited: 23/08/2011 17:24:00 CLOCK Register 1 0x11. Clock Register 1 0x11 Byte Bit 7 Bit 6 Bit 5 Bit 4 B

User Manual SMT941 Page 16 of 43 Last Edited: 23/08/2011 17:24:00 1 Output0 (DAC chc&d clk2) Mode PECL1HISWING Output Divider Enable Default ‘10

User Manual SMT941 Page 17 of 43 Last Edited: 23/08/2011 17:24:00 CLOCK Register 5 0x15. Clock Register 5 0x15 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bi

User Manual SMT941 Page 18 of 43 Last Edited: 23/08/2011 17:24:00 2 ‘10’ 30% output current reduction Setting Bit 9:8 Description BIAS_DIV23 Cur

User Manual SMT941 Page 19 of 43 Last Edited: 23/08/2011 17:24:00 Reset Register 8 0x18 Setting Bit 8 Description HOLD_ON_LOR 0 0 Normal mode

User Manual SMT941 Page 2 of 43 Last Edited: 23/08/2011 17:24:00 Revision History Issue Changes Made Date Initials 1 Original document ‘pre-release

User Manual SMT941 Page 20 of 43 Last Edited: 23/08/2011 17:24:00 0 Reserved BIAS_DIV45 Reserved Default ‘00’ ‘00’ ‘0101’ Reset Register A 0x1A

User Manual SMT941 Page 21 of 43 Last Edited: 23/08/2011 17:24:00 0 ‘0’ Normal mode of operation 1 ‘1’ FB Divider can be started with external NRESE

User Manual SMT941 Page 22 of 43 Last Edited: 23/08/2011 17:24:00 CLOCK Register 10 0x20. Clock Register 10 0x20 Byte Bit 7 Bit 6 Bit 5 Bit 4

User Manual SMT941 Page 23 of 43 Last Edited: 23/08/2011 17:24:00 Setting Bit 11:10 Description Extended lock detect window - LOCKW 0 ‘00’ 1 ‘01’

User Manual SMT941 Page 24 of 43 Last Edited: 23/08/2011 17:24:00 Default ‘00000000’ 0 Reference Divider M[3:0] Reserved Default ‘0000’ ‘1010’ Res

User Manual SMT941 Page 25 of 43 Last Edited: 23/08/2011 17:24:00 1 ‘1’ Secondary reference divider enabled Setting Bit 6 Description FB_DIS 0 ‘0’

User Manual SMT941 Page 26 of 43 Last Edited: 23/08/2011 17:24:00 1 ‘1’ RESET or HOLD acts as nHOLD pin CLOCK Register 18 0x28. Clock Regi

User Manual SMT941 Page 27 of 43 Last Edited: 23/08/2011 17:24:00 ADC Chab Register 0 0x30. ADC Chab Register 0 0x30 Byte Bit 7 Bit 6 B

User Manual SMT941 Page 28 of 43 Last Edited: 23/08/2011 17:24:00 1 ‘1’ Both ADC channels are put into standby mode (internal ref and output buffers

User Manual SMT941 Page 29 of 43 Last Edited: 23/08/2011 17:24:00 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Reserved Channel Control Re

User Manual SMT941 Page 3 of 43 Last Edited: 23/08/2011 17:24:00 Table of Contents Precautions ...

User Manual SMT941 Page 30 of 43 Last Edited: 23/08/2011 17:24:00 Default ‘0’ ‘0000000’ ADC Chab Register 5 0x35 Setting Bit 3:0 Description O

User Manual SMT941 Page 31 of 43 Last Edited: 23/08/2011 17:24:00 ADC Chab Register 6 0x36 Setting Bit 2:0 Description Test Patterns ChA 0 ‘000

User Manual SMT941 Page 32 of 43 Last Edited: 23/08/2011 17:24:00 6 ‘0110’ 16Meg 7 ‘0111’ 32Meg 8 ‘1000’ 64Meg 9 ‘1001’ 128Meg 10 ‘1010’ 256Meg 11 ‘

User Manual SMT941 Page 33 of 43 Last Edited: 23/08/2011 17:24:00 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Reserved Offset Pedestal Ch

User Manual SMT941 Page 34 of 43 Last Edited: 23/08/2011 17:24:00 ADC Chcd Register 1 0x41 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0

User Manual SMT941 Page 35 of 43 Last Edited: 23/08/2011 17:24:00 3 ‘111’ Falling edge shifted by -(4/26)/Sampling Frequency Setting Bit 15:13 Descr

User Manual SMT941 Page 36 of 43 Last Edited: 23/08/2011 17:24:00 0 ‘0’ Offset Correction Disabled. 1 ‘1’ Offset Correction Enabled. ADC Chcd Reg

User Manual SMT941 Page 37 of 43 Last Edited: 23/08/2011 17:24:00 0 128 steps for a range of 0.134dB ADC Chcd Register 6 0x46. ADC Chcd Regi

User Manual SMT941 Page 38 of 43 Last Edited: 23/08/2011 17:24:00 ADC Chcd Register 7 0x47 Setting Bit 6 Description Offset Correction Enable Ch

User Manual SMT941 Page 39 of 43 Last Edited: 23/08/2011 17:24:00 0 128 steps for a range of 0.134dB Setting Bit 10:8 Description Test Patterns C

User Manual SMT941 Page 4 of 43 Last Edited: 23/08/2011 17:24:00 ADC Chab Register 2 – 0x32. ...

User Manual SMT941 Page 40 of 43 Last Edited: 23/08/2011 17:24:00 3 PCB Layout 3.1 Top View 3.2 Bottom View

User Manual SMT941 Last Edited: 23/08/2011 17:24:00 4 Connectors 4.1 Description The following table gathers all connectors on the boar

User Manual SMT941 Page 42 of 43 Last Edited: 23/08/2011 17:24:00 4.2 Location on the board Figure 7 - Connectors

User Manual SMT941 Page 43 of 43 Last Edited: 23/08/2011 17:24:00 5 Physical Properties Dimensions 63.5mm x 106.7mm x 18mm Weight Tbc - 35 grams

User Manual SMT941 Page 5 of 43 Last Edited: 23/08/2011 17:24:00 Table of Figures Figure 1 - SMT942 Block diagram. ...

User Manual SMT941 Page 6 of 43 Last Edited: 23/08/2011 17:24:00 Introduction The SMT941 is a single width expansion TIM that plugs onto an SL

User Manual SMT941 Last Edited: 23/08/2011 17:24:00 1 Related Documents 1.1 Referenced Documents ADC datasheet: Texas Instrument ADS62P49. Cloc

User Manual SMT941 Last Edited: 23/08/2011 17:24:00 2 Functional Description 2.1 Block Diagram SLB Base Module (In this case SMT351T)SMT941 (SL

User Manual SMT941 Page 9 of 43 Last Edited: 23/08/2011 17:24:00 MHz VCXO). The distribution chip also allows synchronising the on-board VCXO to a r